--
--    Copyright (c) 2005 Riad S. Wahby <rsw@jfet.org>
--
--    This file is part of the Weston voltmeter clock code.
--
--    The Weston voltmeter clock code is free software; you can redistribute it and/or modify
--    it under the terms of the GNU General Public License as published by
--    the Free Software Foundation; either version 2 of the License, or
--    (at your option) any later version.
--
--    Foobar is distributed in the hope that it will be useful,
--    but WITHOUT ANY WARRANTY; without even the implied warranty of
--    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
--    GNU General Public License for more details.
--
--    You should have received a copy of the GNU General Public License
--    along with Foobar; if not, write to the Free Software
--    Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
--

pragma target chip          16f628
pragma target clock         10_000_000
pragma target osc           hs
pragma target watchdog      off
pragma target powerup       on
pragma target protection    off
pragma target lowvoltage    off
pragma target mcleario      off
pragma target brownout      on

var volatile byte ccpr1l  at 0x15
var volatile byte ccp1con at 0x17
var volatile bit cp1x at ccp1con : 5
var volatile bit cp1y at ccp1con : 4
var volatile bit ccp1m3 at ccp1con : 3
var volatile bit ccp1m2 at ccp1con : 2
var volatile bit ccp1m1 at ccp1con : 1
var volatile bit ccp1m0 at ccp1con : 0
var volatile byte clkset at 0x70 = 0xC4
var volatile byte sincr  at 0x71 = 1
var volatile byte sechi  at 0x72 = 0
var volatile byte seclo  at 0x73 = 0
var volatile bit seclox at seclo : 7
var volatile bit secloy at seclo : 6
var volatile byte t2con at 0x12
var volatile byte pr2 at 0x92
var volatile byte optionreg at 0x81

include jpic
include intrh

-- set up the ports
port_a_direction = all_input
port_b_direction = 0xF3

assembler
    -- set up the timer
        bcf status_rp1          -- in bank 0
        bcf status_rp0          -- ...
        clrwdt                  -- clear wdt
        clrf tmr0               -- clear tmr0 and prescaler
        bsf status_rp0          -- bank 1
        movlw 0b_1110_1111      -- need to be careful
        movwf optionreg            -- about moving the prescaler
        clrwdt                  -- to the watchdog timer
        movlw 0b_1110_1000      -- now set the prscl to 000
        movwf optionreg            -- ...
        bcf status_rp0          -- back in bank 0
        movf clkset,w           -- get clkset value
        movwf tmr0              -- set initial value

    -- set up PWM
        bsf status_rp0          -- bank 1
        movlw 0xFF              -- FF goes into...
        movwf pr2               -- ...pr2
        bcf status_rp0          -- bank 0
        clrf ccpr1l             -- set duty cycle
        bcf cp1x               -- ...
        bcf cp1y               -- ...
        movlw 0b_0000_0100      -- load config for t2con
        movwf t2con             -- write it into t2con
        movlw 0b_0000_1111      -- load config for ccp1con
        movwf ccp1con           -- write it into ccp1con
        
    -- set up interrupts
        bcf intcon_t0if         -- clear t0if
        bsf intcon_t0ie         -- enable timer interrupt
        bcf intcon_rbif         -- clear rbif
        bsf intcon_rbie         -- enable rb4:7 interrupt
        bsf intcon_gie          -- unmask interrupts
end assembler

forever loop
        asm nop
end loop